Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xix
Figures
Figure
Number Title
Page
Number
Figures
1-1 MPC8308 Block Diagram....................................................................................................... 1-1
1-2 MPC8308 Integrated e300c3 Core Block Diagram ................................................................ 1-9
1-3 USB Controllers Port Configuration..................................................................................... 1-12
2-1 MPC8308 Signal Groupings (1 of 2) ...................................................................................... 2-2
2-2 MPC8308 Signal Groupings (2 of 2) ...................................................................................... 2-3
4-1 Power-On Reset Flow ............................................................................................................. 4-6
4-2 Hard Reset Flow...................................................................................................................... 4-7
4-3 Reset Configuration Word Low Register (RCWLR)............................................................ 4-10
4-4 Reset Configuration Word High Register (RCWHR)........................................................... 4-12
4-5 EEPROM Data Format for Reset Configuration Words Preload Command........................ 4-19
4-6 EEPROM Contents ............................................................................................................... 4-20
4-7 Clock Subsystem Block Diagram ......................................................................................... 4-23
4-8 Reset Status Register (RSR)..................................................................................................4-26
4-9 Reset Mode Register (RMR)................................................................................................. 4-27
4-10 Reset Protection Register (RPR)........................................................................................... 4-28
4-11 Reset Control Register (RCR)............................................................................................... 4-28
4-12 Reset Control Enable Register (RCER)................................................................................ 4-29
4-13 System PLL Mode Register .................................................................................................. 4-30
4-14 Output Clock Control Register (OCCR)............................................................................... 4-31
4-15 System Clock Control Register (SCCR)............................................................................... 4-32
5-1 Local Memory Map Example ................................................................................................. 5-2
5-2 Internal Memory Map Registers’ Base Address Register (IMMRBAR)................................ 5-6
5-3 Alternate Configuration Base Address Register (ALTCBAR) ............................................... 5-7
5-4 LBC Local Access Window n Base Address Registers (LBLAWBAR0–LBLAWBAR3) .... 5-7
5-5 LBC Local Access Window n Attributes Registers (LBLAWAR0–LBLAWAR3) ................ 5-8
5-6 PCI Express 1 Local Access Window Base Address Register (PCIEXP1LAWBAR)........... 5-9
5-7 PCI Express 1 Local Access Window Attributes Register (PCIEXP1LAWAR) .................. 5-10
5-8 DDR Local Access Window n Base Address Registers (DDRLAWBAR0–DDRLAWBAR1)...
5-11
5-9 DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1)....... 5-12
5-10 System General Purpose Register Low (SGPRL)................................................................. 5-16
5-11 System General Purpose Register High (SGPRH) ............................................................... 5-16
5-12 System Part and Revision ID Register (SPRIDR) ................................................................ 5-17
5-13 System Priority Configuration Register (SPCR) .................................................................. 5-18
5-14 System I/O Configuration Register Low (SICRL) ............................................................... 5-20
5-15 System I/O Configuration Register High (SICRH) .............................................................. 5-22
5-16 DDR Control Driver Register (DDRCDR)........................................................................... 5-27
5-17 DDR Debug Status Register (DDRDSR).............................................................................. 5-28