Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-51
Table 5-50 defines the bit fields of PTPSR.
5.5.5.4 Periodic Interval Timer Counter Register (PTCTR)
The periodic interval timer counter register (PTCTR), shown in Figure 5-39, is a read-only register that
shows the current value in the PIT counter. The PTCTR counter is not affected by reads or writes.
Table 5-51 defines the bit fields of PTCTR.
5.5.5.5 Periodic Interval Timer Event Register (PTEVR)
The periodic interval timer event register (PTEVR), shown in Figure 5-40, is used to report the source of
the interrupts. The register can be read at any time. PTEVR bits are cleared by writing ones. Writing zeros
does not affect the value of the status bits.
Table 5-50. PTPSR Bit Settings
Bits Name Description
0–31 PRSC PIT prescaler bits. Selects the input clock divider to generate the PIT counter clock. The prescaler is
programmed to divide the PIT clock input by values from 1 to 4,294,967,296. The value 0x0000 divides the
clock by 1 and 0xFFFF_FFFF divides the clock by 4,294,967,296.
To accurately predict the timing of the next count, change the PRSC bit only when the enable bit PTCNR[CLE]
is clear. Changing PRSC resets the prescaler counter. System reset and the loading of a new value into the
counter also reset the prescaler counter. Clearing the PTCNR[CLE] bit stops the prescaler counter.
Offset 0x0C Access: Read only
0 31
R CNTV
W
Reset All zeros
Figure 5-39. Periodic Interval Timer Counter Register (PTCTR)
Table 5-51. PTCTR Bit Settings
Bits Name Description
0–31 CNTV PIT counter value field. Contains the current value of the time counter. This is a read-only field. Writes have
no effect on PTCTR[CNTV].
Offset 0x10 Access: w1c
0 30 31
R
—
PIF
W w1c
Reset All zeros
Figure 5-40. Periodic Interval Timer Event Register (PTEVR)