Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-50 Freescale Semiconductor
5.5.5.2 Periodic Interval Timer Load Register (PTLDR)
The periodic interval timer load register (PTLDR), shown in Figure 5-37, contains the 32-bit value to be
loaded in a 32-bit PIT counter.
Table 5-49 defines the bit fields of PTLDR.
5.5.5.3 Periodic Interval Timer Prescale Register (PTPSR)
The periodic interval timer prescale register (PTPSR), shown in Figure 5-38, is a read/write register that
used to configure the PIT prescaler’s value.
25 CLIN Input clock control bit. The input clock to the PIT can be either an internal system clock or an external
RTC_PIT_CLOCK.
0 The input clock to the periodic interrupt timer is internal system clock.
1 The input clock to the periodic interrupt timer is external RTC_PIT_CLOCK.
26–30 — Write reserved, read = 0
31 PIM Periodic interrupt mask bit. Used to enable or disable (mask) the PIT periodic interrupt.
0 Periodic interrupt generation disabled.
1 Periodic interrupt generation enabled.
Offset 0x04 Access: Read/Write
0 31
R
CLDV
W
Reset All zeros
Figure 5-37. Periodic Interval Timer Load Register (PTLDR)
Table 5-49. PTLDR Bit Settings
Bits Name Description
0–31 CLDV Contains the 32-bit value to be loaded in a 32-bit PIT counter.
Offset 0x08 Access: Read/Write
0 31
R
PRSC
W
Reset All zeros
Figure 5-38. Periodic Interval Timer Prescale Register (PTPSR)
Table 5-48. PTCNR Bit Settings (continued)
Bits Name Description