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System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-49
5.5.5 PIT Memory Map/Register Definition
The PIT programmable register map occupies 32 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All PIT registers are 32 bits wide and reside on 32-bit address boundaries and should only be accessed as
32-bit quantities.
All addresses used in this chapter are offsets from PIT base, as defined in Chapter 3, “Memory Map.”
Table 5-47 shows the PIT memory map.
5.5.5.1 Periodic Interval Timer Control Register (PTCNR)
The periodic interval timer control register (PTCNR), shown in Figure 5-36, is used to enable the different
PIT functions. The register can be read at any time.
Table 5-48 defines the bit fields of PTCNR.
Table 5-47. PIT Register Address Map
Offset Register Access Reset Value
Section/
Page
Periodic Interval Timer (PIT)—Block Base Address 0x0_0400
0x000 Periodic interval timer control register (PTCNR) R/W 0x0000_0000 5.5.5.1/5-49
0x004 Periodic interval timer load register (PTLDR) R/W 0x0000_0000 5.5.5.2/5-50
0x008 Periodic interval timer prescale register (PTPSR) R/W 0x0000_0000 5.5.5.3/5-50
0x00C Periodic interval timer counter register (PTCTR) R 0x0000_0000 5.5.5.4/5-51
0x010 Periodic interval timer event register (PTEVR) w1c 0x0000_0000 5.5.5.5/5-51
0x014–0x01F Reserved — —
Offset 0x00 Access: Read/Write
0 23 24 25 26 30 31
R
— CLEN CLIN — PIM
W
Reset All zeros
Figure 5-36. Periodic Interval Timer Control Register (PTCNR)
Table 5-48. PTCNR Bit Settings
Bits Name Description
0–23 — Write reserved, read = 0
24 CLEN Clock enable control bit. Controls the counting of the PIT. When the PIT’s clock is disabled, the counter
maintains its old value. When the counter’s clock is enabled, it continues counting using the previous value.
0 Disable counter.
1 Enable counter.