Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-43
5.4.6.2 Real Time Counter Load Register (RTLDR)
The real time counter load register (RTLDR), shown in Figure 5-29, contains the 32-bit value to be loaded
in the 32-bit RTC counter.
Table 5-40 lists the bit field of RTLDR.
5.4.6.3 Real Time Counter Prescale Register (RTPSR)
The real time counter prescale register (RTPSR), shown in Figure 5-30, is a read/write register used to
configure the RTC prescaler’s value.
Table 5-41 lists the bit field of RTPSR.
Offset 0x04 Access: Read/Write
0 31
R
CLDV
W
Reset All zeros
Figure 5-29. Real Time Counter Load Register (RTLDR)
Table 5-40. RTLDR Bit Settings
Bits Name Description
0–31 CLDV Contains the 32-bit value to be loaded in the 32-bit RTC counter.
Offset 0x08 Access: Read/Write
0 31
R
PRSC
W
Reset All zeros
Figure 5-30. Real Time Counter Prescale Register (RTPSR)
Table 5-41. RTPSR Bit Settings
Bits Name Description
0–31 PRSC RTC prescaler bits. Select the input clock divider for the RTC counter clock. The prescaler is programmed to
divide the RTC clock input by values from 1 to 4,294,967,296. The value 0x0000 divides the clock by 1 and
0xFFFF_FFFF divides the clock by 4,294,967,296.
To accurately predict the timing of the next count, change the RTPSR[PRSC] field only when the enable bit
RTCNR[CLE] is clear. Changing the RTPSR[PRSC] bits resets the prescaler counter. RTC reset (for more
information, see Section 5.4.8, “RTC Reset Sequence”) and the loading of a new value into the counter both
reset the prescaler counter. Clearing RTCNR[CLE] stops the prescaler counter.