Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-39
According to the value of SWCRR[SWRI], the WDT timer causes a hard reset or machine check
interrupt to the core.
— Reset mode (SWCRR[SWRI] = 1).
Software watchdog timer causes a hard reset (this is the default value after hard reset).
— Interrupt mode (SWCRR[SWRI] = 0).
Software watchdog timer causes a machine check interrupt to the core.
• WDT prescaled/non-prescaled clock mode
The WDT counter clock can be prescaled by programming the SWCRR[SWPR] bit that controls
the divide-by-65,536 of the WDT counter.
— Prescale mode (SWCRR[SWPR] = 1)
The WDT clock is prescaled.
— Non-prescale mode (SWCRR[SWPR] = 0)
The WDT clock is not prescaled.
5.3.6 Initialization/Application Information (WDT Programming
Guidelines)
The software watchdog timer is enabled (by the default value of SWCRR[SWEN]) after reset. The
following initialization sequence of WDT is required:
• WDT disabling
If the software watchdog timer is not needed, the user must clear SWCRR[SWEN] bit to disable
the WDT not later than its timer times out (~34.36 sec for a 125-MHz system clock).
• WDT initial servicing
If the software watchdog timer is to be used, the special service sequence, described in
Section 5.3.5.1, “Software Watchdog Timer Unit,” must be executed after system reset and not
later than the first WDT time-out (~34.36 sec for a 125-MHz system clock).
Subsequently, periodical WDT servicing should be performed according to the programming
guidelines given in Section 5.3.5.1, “Software Watchdog Timer Unit.”
5.4 Real Time Clock (RTC) Module
This section describes the theory of operation of the real time clock module including a definition of the
external signals and the functions it serves. Additionally, the configuration, control, and status registers are
also described.
5.4.1 Overview
The device platform provides a real time clock (RTC) timer suitable for time stamping or time and calendar
generation. It can maintain a 1-sec count which is unique over a period of approximately 136 years.
The RTC can be initialized by software with an initial count value using the real time counter load register
(RTLDR). It can also be programmed to generate an interrupt every second. The real time counter control