Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-35
Table 5-34 defines the bit fields of SWCRR.
5.3.4.2 System Watchdog Count Register (SWCNR)
The system watchdog count register (SWCNR), shown in Figure 5-23, provides visibility to the watchdog
counter value. The SWCNR is a read-only register. Writes to SWCNR have no effect and terminate
without transfer error exception.
Table 5-34. SWCRR Bit Settings
Bits Name Description
0–15 SWTC Software watchdog time count
The SWTC field contains the modulus that is reloaded into the watchdog counter by a service sequence.
When a new value is loaded into SWCRR[SWTC], the software watchdog timer is not updated until the
servicing sequence is written to the SWSRR. If SWCRR[SWEN] is loaded with 0, the modulus counter
does not count. The new value is also used at the next and all subsequent reloads. Reading the SWCRR
register returns the value in the system watchdog control register. Reset initializes the SWCRR[SWTC]
field to 0xFFFF.
Note: The prescaler counter is reset any time a new value is loaded into the watchdog counter and also
during reset.
16–28 — Write reserved, read = 0
29 SWEN Watchdog enable bit
Enables the watchdog timer. The reset value directly depends on the value of the RCWHR[SWEN] bit. It
should be cleared by software after a system reset to disable the software watchdog timer. When the
watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state.
0 Watchdog timer disabled
1 Watchdog timer enabled
Note: After software writes the SWRI bit, the state of SWEN cannot be changed.
30 SWRI Software watchdog reset/interrupt select bit
A WDT timeout causes either a hard reset or machine check interrupt to the core.
0 Software watchdog timer causes a machine check interrupt to the core
1 Software watchdog timer causes a hard reset
31 SWPR Software watchdog counter prescale bit
Controls the divide-by-65,536 WDT counter prescaler
0 The WDT counter is not prescaled.
1 The WDT counter clock is prescaled.
Offset 0x8 Access: Read only
0151631
R
—
SWCN
W
Reset00000000000000001111111111111111
Figure 5-23. System Watchdog Count Register (SWCNR)