Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-34 Freescale Semiconductor
5.3.4 WDT Memory Map/Register Definition
The WDT programmable register map occupies 16 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros, and writing has no effect.
All WDT registers are 16- or 32-bits wide, located on 16-bit address boundaries, and should be accessed
as 16- or 32-bit quantities. All addresses used in this chapter are offsets from the WDT base, as defined in
Chapter 3, “Memory Map.”
Table 5-33 shows the WDT memory map.
5.3.4.1 System Watchdog Control Register (SWCRR)
The system watchdog control register (SWCRR), shown in Figure 5-22, controls the software watchdog
period and configures watchdog timer operation. The SWCRR can be read at any time but can be written
only once after system reset.
Table 5-33. WDT Register Address Map
Offset Register Access Reset Value Section/ Page
Watchdog Timer (WDT)—Block Base Address 0x0_0200
0x000–0x003 Reserved — — —
0x004 System watchdog control register (SWCRR) R/W 0xFFFF_0003
or 0xFFFF_0007
1
1
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
5.3.4.1/5-34
0x008 System watchdog count register (SWCNR) R 0x0000_FFFF 5.3.4.2/5-35
0x00C–0x00D Reserved — — —
0x00E System watchdog service register (SWSRR) R/W 0x0000 5.3.4.3/5-36
Offset 0x4 Access: Read/Write
0 1516 28293031
R
SWTC — SWEN SWRI SWPR
W
Reset11111111111111110000000000000 0
1
11
1
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
Figure 5-22. System Watchdog Control Register (SWCRR)