Information

System Configuration

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 5-33

Figure 5-21 shows a high-level block diagram of the WDT.

Figure 5-21. Software Watchdog Timer High-Level Block Diagram

The software watchdog timer is enabled after reset to cause a hardware reset if it times out. The user has

the option of disabling the software watchdog if it is not needed. If used, the software watchdog timer

requires a special service sequence to be executed periodically. Without this periodic servicing, the

software watchdog timer times out and issues a reset or a non-maskable interrupt.

5.3.2 WDT Features

The WDT includes the following key features:

• Based on 16-bit prescaler and 16-bit down-counter

• Provides a selectable range for the time-out period

• Provides ~34.36 sec maximum software time-out delay for 125-MHz input clock

• Functional and programming compatibility with MPC8260 watchdog timer

5.3.3 WDT Modes of Operation

The WDT unit can operate in the following modes:

• WDT enable/disable mode

If the software watchdog timer is not needed, the user can disable it with software after a system

reset. When the watchdog timer is disabled, the watchdog counter and prescaler counter are held

in a stopped state.

• WDT output reset/interrupt mode

Without software periodic servicing, the software watchdog timer times out and issues a reset or a

nonmaskable interrupt (mcp)

• WDT prescaled/non-prescaled clock mode

The WDT counter clock can be prescaled by programming the SWCRR[SWPR] bit, which

controls the divide-by-65,536 of the WDT counter.

Software

Reset

or mcp

System

Watchdog

clock

Timer