Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-32 Freescale Semiconductor
5.2.2.13 RTC Control Registers (RTCCR)
The RTC control register controls the reset for the RTC.
Figure 5-20 shows the RTCCR bit settings.
Table 5-32 describes the bits of the RTCCR register.
5.3 Software Watchdog Timer (WDT)
The following sections describe the theory of operation of the software watchdog timer (WDT) in the
device, including a definition of the external signals and the functions they serve. Additionally, the
configuration, control, and status registers are also described. Note that individual chapters in this book
describe specific initialization aspects for each individual block.
5.3.1 WDT Overview
The device provides a software watchdog timer (WDT) feature to prevent system lock in case the software
becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the system
watchdog control register (SWCRR).
The watchdog counter is a free-running down-counter that generates a reset or a non-maskable interrupt
on underflow. To prevent a reset, software must periodically restart the countdown. The WDT is
responsible for asserting a hardware reset or machine-check interrupt (mcp) if the software fails to service
the software watchdog timer for a certain period of time (for example, because software is lost or trapped
in a loop with no controlled exit).
Offset 0x00148 Access: Read/Write
0 15
R
—
W
Reset All zeros
16 30 31
R
— RESET_RTC
W
Reset All zeros
Figure 5-20. RTC Control Register (RTCCR)
Table 5-32. RTCCR Field Description
Bits Name Description
0–30 Reserved —
31 RESET_RTC Reset RTC
1 Software needs to assert this bit to reset the RTC logic and then negate this bit to allow the RTC
logic to operate normally.
Note that this register is reset by Power On Reset or HRESET, but RTC is not initialized during
Power On Reset or HRESET.
0 Deassert reset to the RTC
For more information, see Section 15.8.1.1, “RTC Reset Sequence.”