Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-31
Table 5-31 describes the bits of the SDHCCR register.
Table 5-31. SDHCCR Field Description
Bits Name Description
0 RD_PREFETCH_VAL This determines the prefetch byte count to be used if RD_PREFETCH_DISABLE is
not set.
0 32 byte prefetch
1 64 byte prefetch
1 RD_PREFETCH_DISABLE Read prefetch disable. This should be cleared if the target of read DMA operation
is a well-behaved memory that is not affected by the read operation and returns the
same data if read again from the same location. This means that prefetch of data
can be done by the internal bus units, and it results in faster read completion.
0 It is allowed to prefetch data on DMA read operation
1 It is not allowed to prefetch data on DMA read operation
2 RD_SAFE_ENABLE Read Safe enable. This bit should be set only if the target of read DMA operation is
a well-behaved memory that is not affected by the read operation and returns the
same data if read again from the same location. This means that unaligned reading
operation can be rounded up to enable more efficient read operations.
0 It is not safe to read more bytes that were intended
1 It is safe to read more bytes that were intended
3 DMA_W_CTRL Write delay control bit.
0 No delay
1 Delay the Write/Read transaction till the interrupt is active
4 ERROR_DISABLE Ignore or react to bus errors.
0 React to bus transaction errors
1 Ignore bus transaction errors
5—Reserved
6 SNOOP_ENABLE Snoop attribute.
0 DMA transactions are not snooped by e300 CPU data cache
1 DMA transactions are snooped by e300 CPU data cache
7–13 Reserved —
14–15 PRIORITY_CTRL Priority. This field is used to present priority level for CSB arbitration for eSDHC
DMA requests.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
16–31 Reserved —