Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-30 Freescale Semiconductor
5.2.2.12 eSDHC Control Registers (SDHCCR)
The eSDHC control registers can be used to control various settings that affect the priority and DMA
operations. SDHCCR1 is located at offset 0x144.
Figure 5-19 shows the SDHCCR bit settings.
28–29 PRI_DES DMA descriptor priority. This field is used to present priority level for CSB arbitration for PCI Express
controller’s DMA requests. Bits 28–29 are used when the request belongs to descriptor fetch or update.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
30–31 PRI_PIO PIO priority. This field is used to present priority level for CSB arbitration for PCI Express controller’s
PIO inbound requests.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
Offset 0x00144 Access: Read/Write
0 1 2 34567 131415
R
RD_P
REFE
TCH_
VAL
RD_PR
EFETC
H_DISA
BLE
RD_S
AFE_
ENAB
LE
DMA
_W_
CTRL
ERR
OR_
DISA
BLE
—
SNO
OP_E
NABL
E
—
PRIORITY_
CTRL
W
Reset All zeros
16 31
R
—
W
Reset All zeros
Figure 5-19. eSDHC Control Register (SDHCCR)
Table 5-30. PECR Field Description (continued)
Bits Name Description