Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-29
Figure 5-18 shows the PECR bit settings.
Table 5-30 describes the bits of the PECR register.
Offset 0x00140 Access: Read/Write
0123 15
R
LINK_RST CBRST CSR_RST —
W
Reset All zeros
16 17 25 26 27 28 29 30 31
R
DEV_TYPE — PRI_DATA PRI_DES PRI_PIO
W
Reset All zeros
Figure 5-18. PCI Express Controller Registers (PECR1)
Table 5-30. PECR Field Description
Bits Name Description
0 LINK_RST Link soft reset (active low). Assert soft reset to PCI Express controller’s logic that is related to the link,
the configuration registers, and the core logic. Should be negated after device type is programmed and
the SerDes initialization is completed.
0 Link soft reset is asserted
1 Link soft reset is negated
1 CBRST CSB bridge soft reset (active low). Assert soft reset to PCI Express controller’s logic related to the CSB
bridge. Should be negated after device type is programmed and the SerDes initialization is completed.
The CSB bridge soft reset should be asserted also when hot reset is detected, in order to clean the
queues of the CSB interface.
0 CSB bridge soft reset is asserted
1 CSB bridge soft reset is negated
2 CSR_RST CSR soft reset (active low). Assert soft reset to PCI Express controller’s logic that is related to the CSR
(control and status) registers. Should be negated after device type is programmed and the SerDes
initialization is completed.
0 CSR soft reset is asserted
1 CSR soft reset is negated
3–15 — Reserved
16 DEV_TYPE Device type. Program device type.
0 EP (end point)
1 RC (root complex)
17–25 — Reserved
26–27 PRI_DATA Data priority. This field is used to present priority level for CSB arbitration for PCI Express controller’s
DMA requests. Bits 26–27 are used when the request belongs to data transfer.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)