Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-28 Freescale Semiconductor
5.2.2.10 DDR Debug Status Register (DDRDSR)
Figure 5-17 contains the debug status bits from the DDR SDRAM controller.
Table 5-29 shows the bit settings of the DDRDSR.
5.2.2.11 PCI Express Control Registers (PECR1)
The PCI Express control registers can be used to control various settings that affect the system response
to PCI Express controller DMA operations or PIO inbound operation. Those registers also control soft
reset assertion and negation to various logic parts of the PCI Express controllers. Note that PECR1
programming controls the behavior of PCI Express controller for port 1. PECR1 is located at offset 0x140.
30 M_odr Disable memory transaction reordering
0 Memory transaction reordering enabled
1 Memory transaction reordering disabled
31 — Reserved
Offset 0x0012C Access: Read
012 56 910 31
R — PZ NZ —
W
Reset00110011000000000000000000000000
Figure 5-17. DDR Debug Status Register (DDRDSR)
Table 5-29. DDRDSR Field Descriptions
Bits Name Description
0–1 — Reserved
2–5 PZ Current setting of PFET driver impedance
0000 Half strength—highest Z
1000 Higher Z than nominal
1100 Nominal impedance setting
1110 Lower Z than nominal
1111 Much lower Z than nominal
6–9 NZ Current setting of NFET driver impedance
0000 Half strength—highest Z
1000 Higher Z than nominal
1100 Nominal impedance setting
1110 Lower Z than nominal
1111 Much lower Z than nominal
10–31 — Reserved
Table 5-28. DDRCDR Field Descriptions (continued)
Bits Name Description