Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-27
DDRCDR is shown in Figure 5-16.
Table 5-28 shows the bit definition of the DDRCDR.
Offset 0x00128 Access: Read/Write
0 1 2 5 6 9 10 11 12 13 14 15
R
— DSO_EN DSO_PZ DSO_NZ — ODT
DDR_TYPE
(Reserved to 0)
—
W
Reset 0 0 0000 0 0 0 0 0 0 0 0 0 0
16 28 29 30 31
R
— MVREF_SEL M_odr —
W
Reset 0 0 0000 0 0 0 0 0 0 0 0 0 0
Figure 5-16. DDR Control Driver Register (DDRCDR)
Table 5-28. DDRCDR Field Descriptions
Bits Name Description
0—Reserved
1 DSO_EN 0 DDR driver software override disable
1 DDR driver software override enable
2–5 DSO_PZ DDR driver software p-impedance override
0000 Half strength—Highest Z
1000 Much higher Z than nominal
1100 Higher Z than nominal
1110 Nominal impedance setting
1111 Lower Z than nominal
6–9 DSO_NZ DDR driver software n-impedance override
0000 Half strength—Highest Z
1000 Much higher Z than nominal
1100 Higher Z than nominal
1110 Nominal impedance setting
1111 Lower Z than nominal
10–11 — Reserved. Should be cleared.
12 ODT ODT termination value for I/Os
075 
1 150 
13 DDR_TYPE Selects voltage level for DDR pads
0 DDR2 (1.8V mode) nominal impedance—18 
1 DDR1 (2.5V mode) nominal impedance—18 
Note: DDR_TYPE must be set according to the logical type of the DDR memory devices, as it affects
logic behavior of the DDR controller as well as the physical parameters of the DDR I/O pads.
14–28 — Reserved
29 MVREF_SEL MVREF_SEL
0 MVREF is i/p from external source
1 MVREF is generated internally from GVDD