Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-22 Freescale Semiconductor
5.2.2.6 System I/O Configuration Register High (SICRH)
The system I/O configuration register high (SICRH), shown in Figure 5-15, controls the multiplexing of
the rest of the device I/O pins. Each bit or set of bits in this register selects which function is used by a
certain group of the device pins.
Table 5-26 defines the bit fields of SICRH. Each Pin Function column lists the name of the multi-function
pin used in this option. Note that the groups have two control bits to program the pin functionality.
Note that bits 30 and 31 (TSOBI1and TSOBI2), which control TSEC output buffer impedance, are
described in Table 5-27.
Offset 0x00118 Access: Read/Write
01234567
R
eSDHC_A eSDHC_B eSDHC_C GPIO_A
W
Reset00000000
8 9 10 11 12 13 14 15
R
GPIO_B IEEE1588_A USB GTM
W
Reset00010100
16 17 18 19 20 22 23
R
IEEE1588_B ETSEC2 — GPIO_SEL
W
Reset01010000
24 26 27 28 29 30 31
R
— TMROBI — TSOBI1 TSOBI2
W
Reset
000000
depends on
RCW
0
Figure 5-15. System I/O Configuration Register High (SICRH)
Table 5-26. SICRH Bit Settings
SICRH[Bits] Value 0b00 0b01 0b10 0b11
Reset
Value
Bits Group Pin Function 0 Pin Function 1 Pin Function 2 Pin Function 3
0–1 eSDHC_A
1
SD_CLK
2
——GPIO_1600
SD_CMD — — GPIO_17
SD_CD GTM1_TIN1 — GPIO_18
SD_WP GTM1_TGATE1 —GPIO_19
2–3 eSDHC_B SD_DAT0 GTM1_TOUT1
—GPIO_2000
SD_DAT1 GTM1_TOUT2 —GPIO_21