Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-19
5.2.2.5 System I/O Configuration Register Low (SICRL)
The system I/O configuration register low (SICRL) controls the multiplexing of some of the device I/O
pins. Each bit or set of bits in the SICRL selects which function is used by a certain group of the device
pins.
The reset value of this register depends on TSEC1M fields setting in the reset configuration word high.
The function of these pins can be changed by writing to this register during system initialization. TSOBI1
reset value also depends on the TSEC1M field settings in the reset configuration word high in order to
select the correct output buffer impedance for full or reduced TSEC pin mode.
20–21 TSECBDP eTSEC buffer descriptor priority.
Selects the CSB request priority driven by eTSEC1 and eTSEC2 when they require to transfer a buffer
descriptor (BD) on this bus. The level of priority can be chosen from four possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority
22–23 TSECEP TSEC emergency priority. Selects the CSB request priority driven by eTSEC1 and eTSEC2 when an
emergency condition occurs. The level of priority can be chosen from four possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
24–31 — Reserved. Should be cleared.
Table 5-24. SPCR Bit Settings (continued)
Bits Name Description