Information
System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-18 Freescale Semiconductor
whenever an internal unit requests mastership of the coherent system bus (CSB). The SPCR also includes
some other control functions.
Table 5-24 defines the bit fields of SPCR.
‘
Offset 0x00110 Access: Read/Write
01 2 3 789101112 15
R
—
EN_SEONAK_
FIX
OPT TBEN COREPR —
W
Reset All zeros
16 17 18 19 20 21 22 23 24 31
R
— TSECDP TSECBDP TSECEP —
W
Reset All zeros
Figure 5-13. System Priority Configuration Register (SPCR)
Table 5-24. SPCR Bit Settings
Bits Name Description
0–1 — Reserved. Should be cleared.
2EN_
SEONAK_FIX
enable_se0nak_fix for USBDR
If set, disables the SOF reporting when in SE0_NAK test mode.
3–7 — Reserved. Should be cleared.
8 OPT Optimize. Setting this bit may enhance the performance of transactions issued to the internal coherent
system bus (CSB) by a master such as USB controller. Performance is enhanced by reading more
bytes on the bus than actually needed by the master in the case that this is more efficient. The user
may set this bit only if it is known that USB transactions sent to the internal CSB are not accessing
devices in which speculative reads may change the state of the device (for example, FIFOs in which
reading a byte may advance some internal counter).
0 No performance enhancement.
1 Performance enhancement by speculative reading is enabled.
9 TBEN e300 core time base unit enable
0 Time base unit is disabled.
1 Time base unit is enabled.
10–11 COREPR e300 core CSB request priority.
The priority level for the core in accessing the CSB can be chosen from four possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
12–17 — Reserved. Should be cleared
18-19 TSECDP eTSEC Data Priority.
Selects the CSB request priority driven by eTSEC1 and eTSEC2 when it requires to transfer data on
this bus.
The level of priority can be chosen from four possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)