Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-14 Freescale Semiconductor
The PCI Express interface has outbound address translation units that map the local address into an
external address space.
These other mapping functions are configured by programming the configuration, control, and status
registers of the individual interfaces. Note that there is no need to have a one-to-one correspondence
between local access windows and chip select regions or outbound windows. A single local access window
can be further decoded to any number of chip-selects or to any number or outbound windows at the target
interface.
5.1.8 Outbound Address Translation and Mapping Windows
Outbound address translation and mapping refers to the translation of addresses from the local 32-bit
address space to the external address space and attributes of a particular I/O interface. On this device, the
PCI Express block has an outbound address translation unit.
5.1.9 Inbound Address Translation and Mapping Windows
Inbound address translation and mapping refers to the translation of an address from the external address
space of an I/O interface (such as PCI Express address space) to the local address space understood by the
internal interfaces of this processor. It also refers to the mapping of transactions to a particular target
interface and the assignment of transaction attributes. The PCI Express controller has inbound address
translation unit.
5.1.9.1 PCI Express Inbound Windows
The PCI Express controller has four inbound windows. In the PCI Express EP (End Point) mode, these
windows are same as the base address registers in the PCI Express programming model. In the PCI Express
RC (Root Complex) mode, there are four separate registers, PEX_RCIWBARL[0:3]. For more
information, see Section 14.6.1.1, “Address Translation Windows (ATMUs).”
5.1.10 Internal Memory Map
All of the memory-mapped configuration, control, and status registers in the device are contained within
a 1-Mbyte address region, referred as the IMMR. To allow for flexibility, the internal memory map block
can be relocated in the local address space. The local address map location of this register block is
controlled by the internal memory map registers’ base address register (IMMRBAR); see Section 5.1.4.1,
“Internal Memory Map Registers Base Address Register (IMMRBAR).” The default value for the
IMMRBAR is 0xFF40_0000.
NOTE
The internal memory map window is always the highest priority local access
window.