Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor xv
Figures
Figure
Number Title
Page
Number
16.5.2 Detailed Memory Map............................................................................................. 16-10
16.5.3 Memory-Mapped Register Descriptions.................................................................. 16-21
16.6 Functional Description............................................................................................... 16-120
16.6.1 Connecting to Physical Interfaces on Ethernet...................................................... 16-121
16.6.2 Gigabit Ethernet Controller Channel Operation.................................................... 16-124
16.6.3 TCP/IP Off-Load ................................................................................................... 16-139
16.6.4 Quality of Service (QoS) Provision....................................................................... 16-144
16.6.5 Lossless Flow Control ........................................................................................... 16-154
16.6.6 Hardware Assist for IEEE Std. 1588 Compliant Timestamping ........................... 16-157
16.6.7 Buffer Descriptors.................................................................................................. 16-164
16.7 Initialization/Application Information....................................................................... 16-171
16.7.1 Interface Mode Configuration ............................................................................... 16-172
16.7.2 MAC: Half-Duplex Collision on FCS of Short Frame.......................................... 16-178
Chapter 17
I
2
C Interface
17.1 Introduction.................................................................................................................... 17-1
17.1.1 Features...................................................................................................................... 17-2
17.1.2 Modes of Operation ................................................................................................... 17-2
17.2 External Signal Descriptions ......................................................................................... 17-3
17.2.1 Signal Overview ........................................................................................................ 17-3
17.2.2 Detailed Signal Descriptions ..................................................................................... 17-3
17.3 Memory Map/Register Definition ................................................................................. 17-4
17.3.1 Register Descriptions................................................................................................. 17-5
17.4 Functional Description................................................................................................. 17-10
17.4.1 Transaction Protocol ................................................................................................ 17-10
17.4.2 Arbitration Procedure .............................................................................................. 17-14
17.4.3 Handshaking ............................................................................................................ 17-15
17.4.4 Clock Control........................................................................................................... 17-15
17.4.5 Boot Sequencer Mode.............................................................................................. 17-16
17.5 Initialization/Application Information......................................................................... 17-21
17.5.1 Interrupt Service Routine Flowchart........................................................................ 17-21
17.5.2 Initialization Sequence............................................................................................. 17-23
17.5.3 Generation of START .............................................................................................. 17-23
17.5.4 Post-Transfer Software Response............................................................................ 17-23
17.5.5 Generation of STOP................................................................................................. 17-24
17.5.6 Generation of Repeated START .............................................................................. 17-24
17.5.7 Generation of SCL When SDA is Negated ............................................................. 17-24
17.5.8 Slave Mode Interrupt Service Routine..................................................................... 17-24