Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-13
Table 5-16 defines the reset value DDRLAWAR0[EN] and DDRLAWAR0[SIZE].
‘
5.1.5 Precedence of Local Access Windows
If two local access windows overlap, the lower numbered window takes precedence (see Table 5-1 for
window numbers). For instance, if two windows are set up as shown in Table 5-17, local access window 1
governs the mapping of the 1-Mbyte region from 0x7FF0_0000 to 0x7FFF_FFF, even though the window
described in local access window 7 also encompasses that memory region.
5.1.6 Configuring Local Access Windows
After a local access window is enabled, it should not be modified while any device in the system may be
using the window. Accordingly, a new window should not be used until the effect of the write to the
window is visible to all blocks that use the window. This can be guaranteed by completing a read of the
last local access window configuration register before enabling any other devices to use the window. For
instance, if local bus local access windows 1–3 are being configured in order during the initialization
process, the last write (to LBLAWAR3) should be followed by a read of LBLAWAR3 before any devices
try to use any of these windows. If the configuration is being done by the local e300 core, the read of
LBLAWAR3 should be followed by an isync instruction.
5.1.7 Distinguishing Local Access Windows from Other Mapping
Functions
It is important to distinguish between the mapping function performed by the local access windows and
the additional mapping functions that happen at the target interface. The local access windows define how
a transaction is routed through the device internal interconnects from the transaction’s source to its target.
Once the transaction has arrived at its target interface, that interface controller may perform additional
mapping. For instance, the DDR SDRAM controller has chip-select registers that map a memory request
to a particular external device. The local bus controller has base registers that perform a similar function.
Table 5-16. DDRLAWAR0[EN] Reset Value
RCWHR[ROMLOC] RLEXT
1
1
For more information, see Section 4.3.2.2, “Reset Configuration Word High Register (RCWHR).”
DDRLAWAR0[EN]
Reset Value
Description
000 00 1 e300 core boot performed from a DDR SDRAM device. DDR
8-Mbyte (2
(22+1)
) local access window is enabled.
000 01 0 e300 core boot not performed from a DDR SDRAM device
Else – 0 e300 core boot not performed from a DDR SDRAM device.
Table 5-17. Overlapping Local Access Windows
Window Base Address Size Target Interface
1 0x7FF0_0000 1 Mbyte Local bus
7 0x0000_0000 2 Gbytes DDR SDRAM