Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-12 Freescale Semiconductor
5.1.4.8 DDR Local Access Window n Attributes Registers
(DDRLAWAR0–DDRLAWAR1)
The DDR local access window n attributes registers (DDRLAWAR0–DDRLAWAR1) are shown in
Figure 5-9.
Table 5-15 defines the bit fields of DDRLAWAR0–DDRLAWAR1.
‘
5.1.4.8.1 DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value
The core may use a DDR SDRAM device to fetch its boot vector. For this purpose an 8-Mbyte (2
(22+1)
)
local access window is defined by DDRLAWBAR0[SIZE] reset value, and DDRLAWAR0 is enabled
according to the value set in the reset configuration word high ROMLOC field.
Offset 0xA4
0xAC
Access: Read/Write
01 25 26 31
R
EN — SIZE
W
Reset All zeros
1,2
1
The reset value of DDRLAWAR0[EN] depends on the reset configuration word high values. See Section 5.1.4.8.1,
“DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,” for a detailed description.
2
The reset value of DDRLAWAR0[SIZE] is always 0b010110, meaning an 8-Mbyte local access window. See Section 5.1.4.8.1,
“DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,” for a detailed description.
Figure 5-9. DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1)
Table 5-15. DDRLAWAR0–DDRLAWAR1 Bit Settings
Bits Name Description
0 EN 0 The DDR local access window n is disabled.
1 The DDR local access window n is enabled and other DDRLAWARn and DDRLAWBARn fields combine
to identify an address range for this window.
1–25 — Reserved. Write has no effect, read returns 0.
26–31 SIZE Identifies the size of the window from the starting address. Window size is 2
(SIZE+1)
bytes.
000000–001010 Reserved. Window is undefined.
001011 4 Kbytes
001100 8 Kbytes
001101 16 Kbytes
. . . . . . . 2
(SIZE+1)
bytes
011110 2 Gbytes
011111–111111 Reserved. Window is undefined.