Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-11
5.1.4.7 DDR Local Access Window n Base Address Registers
(DDRLAWBAR0–DDRLAWBAR1)
The DDR local access window n base address registers (DDRLAWBAR0–DDRLAWBAR1) are shown
in Figure 5-8.
Table 5-13 defines the bit fields of DDRLAWBAR0–DDRLAWBAR1.
‘
5.1.4.7.1 DDRLAWBAR0[BASE_ADDR] Reset Value
The core may use a DDR SDRAM device to fetch its boot vector. For this purpose, the
DDRLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration
word high BMS field.
Table 5-14 defines the reset value DDRLAWBAR0.
Offset 0xA0
0xA8
Access: Read/Write
0 19 20 31
R
BASE_ADDR —
W
Reset All zeros
1
1
The reset value of DDRLAWBAR0[BASE_ADDR] depends on the reset configuration word high values. See Section 5.1.4.7.1,
“DDRLAWBAR0[BASE_ADDR] Reset Value,” for a detailed description
Figure 5-8. DDR Local Access Window n Base Address Registers (DDRLAWBAR0–DDRLAWBAR1)
Table 5-13. DDRLAWBAR0–DDRLAWBAR1 Bit Settings
Bits Name Description
0–19 BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window n. The specified
base address should be aligned to the window size, as defined by DDRLAWARn[SIZE].
20–31 — Reserved. Write has no effect, read returns 0.
Table 5-14. DDRLAWBAR0[BASE_ADDR] Reset Value
RCWHR[BMS]
DDRLAWBAR0[BASE_ADDR]
Reset Value
0 0x00000
1 0xFF800