Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-9
5.1.4.4.1 LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value
The core may use a local bus peripheral device to fetch its boot vector. For this purpose an 8-Mbyte
(2
(22+1)
) local access window is defined by the LBLAWBAR0[SIZE] reset value, and LBLAWAR0 is
enabled according to the value set in the reset configuration word high ROMLOC field.
Table 5-10 defines the reset value for LBLAWAR0[EN].
‘
5.1.4.5 PCI Express Local Access Window Base Address Register
(PCIEXP1LAWBAR)
The PCI Express 1 local access window base address register is shown in Figure 5-6.
1–25 — Reserved. Write has no effect, read returns 0.
26–31 SIZE Identifies the size of the window from the starting address. Window size is 2
(SIZE+1)
bytes.
000000–001010 Reserved. Window is undefined.
001011 4 Kbytes
001100 8 Kbytes
001101 16 Kbytes
. . . . . . . 2
(SIZE+1)
bytes
011110 2 Gbytes
011111–111111 Reserved. Window is undefined.
Table 5-10. LBLAWAR0[EN] Reset Value
RCWHR[ROMLOC] RLEXT
1
1
For more information, see Section 4.3.2.2, “Reset Configuration Word High Register (RCWHR).”
LBLAWAR0[EN]
Reset Value
Description
000 01 1 e300 core boot not performed from a local bus device.
101 00
01
110 00
others 0 e300 core boot performed from a local bus device. Local bus
8-Mbyte (2
(22+1)
) local access window is enabled.
Offset 0x80 Access: Read/Write
0 19 20 31
R
BASE_ADDR —
W
Reset All zeros
Figure 5-6. PCI Express 1 Local Access Window Base Address Register (PCIEXP1LAWBAR)
Table 5-9. LBLAWAR0–LBLAWAR3 Bit Settings (continued)