Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-8 Freescale Semiconductor
Table 5-7 defines the bit fields of LBLAWBAR0–LBLAWBAR3.
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5.1.4.3.1 LBLAWBAR0[BASE_ADDR] Reset Value
The core may also use a local bus peripheral device to fetch its boot vector. For this purpose, the
LBLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word
high BMS field.
Table 5-8 defines the reset value of LBLAWBAR0[BASE_ADDR].
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5.1.4.4 LBC Local Access Window n Attributes Registers
(LBLAWAR0–LBLAWAR3)
The LBC local access window n attributes registers (LBLAWAR0–LBLAWAR3) are shown in Figure 5-5.
Table 5-9 defines the bit fields of LBLAWAR0–LBLAWAR3.
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Table 5-7. LBLAWBAR0–LBLAWBAR3 Bit Settings
Bits Name Description
0–19 BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window n. The specified
base address should be aligned to the window size, as defined by LBLAWARn[SIZE].
20–31 — Reserved. Write has no effect, read returns 0.
Table 5-8. LBLAWBAR0[BASE_ADDR] Reset Value
RCWHR[BMS] BASE_ADDR Reset Value
0 0x00000
10xFF800
Offset 0x24, 0x2C, 0x34, 0x3C Access: Read/Write
01 25 26 31
R
EN — SIZE
W
Reset 0
1
1
The LBLAWAR0[EN] reset value depends on the reset configuration word high values. See Section 5.1.4.4.1, “LBLAWAR0[EN]
and LBLAWAR0[SIZE] Reset Value,” for a detailed description.
0000000000000000000000000000000
2
2
The LBLAWAR0[SIZE] reset value is always 0b010110, meaning an 8-Mbyte local access window. See Section 5.1.4.4.1,
“LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value,” for a detailed description.
Figure 5-5. LBC Local Access Window n Attributes Registers (LBLAWAR0–LBLAWAR3)
Table 5-9. LBLAWAR0–LBLAWAR3 Bit Settings
Bits Name Description
0 EN 0 Local bus local access window n is disabled.
1 Local bus local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields combine to
identify an address range for this window.