Information

System Configuration

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

5-6 Freescale Semiconductor

memory map register is 0xFF40_0000. Because IMMRBAR is at offset 0x0 from the beginning of the

local access registers, the IMMRBAR always points to itself.

5.1.4.1.1 Updating IMMRBAR

Updates to IMMRBAR that relocate the entire 1-Mbyte region of the internal memory block require

special treatment. The effect of the update must be guaranteed to be visible by the mapping logic before

an access to the new location is seen. To make sure this happens, the following guidelines should be

followed:

• IMMRBAR should be updated during initial configuration of the device when only one host or

controller has access to the device as follows:

— If the core is initializing the device, it should set IMMRBAR to the desired final location before

enabling other I/O devices to access the device.

• When the e300 core is writing to IMMRBAR, it should use the following sequence:

— Read the current value of IMMRBAR using a load word instruction followed by an isync. This

forces all accesses to configuration space to complete.

— Write the new value to IMMRBAR.

— Perform a load of an address that does not access configuration space or the on-chip SRAM,

but has an address mapping already in effect (for example, boot ROM). Follow this load with

an isync.

— Read the contents of IMMRBAR from its new location, followed by another isync.

The IMMRBAR is shown in Figure 5-2.

Table 5-5 defines the bit fields of IMMRBAR.

‘

Offset 0x00 Access: User Read/Write

0 11 12 15

BASE_ADDR —

16 31

—

Reset All zeros

Figure 5-2. Internal Memory Map Registers’ Base Address Register (IMMRBAR)

Table 5-5. IMMRBAR Bit Settings

Bits Name Description

0–11 BASE_ADDR Identifies the 12 most-significant address bits of the base of the 1-Mbyte internal memory window.

12–31 — Reserved. Software must write all zeros.