Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-5
5.1.4 Local Access Register Descriptions
This section describes the local access registers.
5.1.4.1 Internal Memory Map Registers Base Address Register (IMMRBAR)
The IMMR window contains configuration, control, and status registers, as well as internal device memory
arrays. The internal memory map occupies a 1-Mbyte region of memory space. Its location is
programmable using the internal memory map register (IMMR). The default base address for the internal
0x0_0030 eLBC local access window 2 base address register
(LBLAWBAR2)
R/W 0x0000_0000 5.1.4.3/5-7
0x0_0034 eLBC local access window 2 attribute register (LBLAWAR2) R/W 0x0000_0000 5.1.4.4/5-8
0x0_0038 eLBC local access window 3 base address register
(LBLAWBAR3)
R/W 0x0000_0000 5.1.4.3/5-7
0x0_003C eLBC local access window 3 attribute register (LBLAWAR3) R/W 0x0000_0000 5.1.4.4/5-8
0x0_0040–0x0_0063 Reserved — — —
0x0_0064 Reserved — — —
0x0_0068–0x0_007C Reserved — — —
0x0_0080 PCI Express local access window base address register
(PCIEXP1LAWBAR)
R/W 0x0000_0000 5.1.4.5/5-9
0x0_0084 PCI Express local access window attribute register
(PCIEXP1LAWAR)
R/W 0x0000_0000 5.1.4.6/5-10
0x0_0088–0x0_009C Reserved — — —
0x0_00A0 DDR2 local access window 0 base address register
(DDRLAWBAR0)
R/W 0x0000_0000
3
5.1.4.7/5-11
0x0_00A4 DDR2 local access window 0 attribute register
(DDRLAWAR0)
R/W 0x0000_0000
4
5.1.4.8/5-12
0x0_00A8 DDR2 local access window 1 base address register
(DDRLAWBAR1)
R/W 0x0000_0000 5.1.4.7/5-11
0x0_00AC DDR2 local access window 1 attribute register
(DDRLAWAR1)
R/W 0x0000_0000 5.1.4.8/5-12
0x0_00B0–0x0_00FC Reserved — — —
1
Depends on reset configuration word high values. See Section 5.1.4.3.1, “LBLAWBAR0[BASE_ADDR] Reset Value,” for details.
2
Depends on reset configuration word high values. See Section 5.1.4.4.1, “LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value,”
for details.
3
Depends on reset configuration word high values. See Section 5.1.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,” for
details.
4
Depends on reset configuration word high values. See Section 5.1.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset
Value,” for details.
Table 5-4. Local Access Register Memory Map (continued)
Local Access—Block Base Address 0x0_0000
Local Memory
Offset (Hex)
Register Access Reset Section/Page