Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-4 Freescale Semiconductor
0xFF40_0000, and this base address value can be modified by writing to this register. For more
information, see Section 5.1.4.1, “Internal Memory Map Registers Base Address Register (IMMRBAR).”
NOTE
Although it is legal to use the 3-Mbyte space consecutive to the 1 Mbyte of
the IMMR (for example, if IMMRBAR is 0xFF40_0000, the 3-Mbyte
address space consecutive to it is 0xFF50_0000–0xFF7F_FFFF), it is not
recommended. This space may be used in future derivatives of the device
that require a larger internal memory space.
5.1.3 Local Access Windows
As demonstrated in the address map overview in Section 5.1, “Local Memory Map Overview and
Example,” local access windows associate a range of the local 32-bit address space with a particular target
interface. This allows the internal interconnections of the device to route a transaction from its source to
the proper target. No address translation is performed. The base address defines the high-order address bits
that give the location of the window in the local address space. The window attributes enable the window
and define its size, while the window number specifies the target interface.
With the exception of configuration space (mapped by IMMRBAR), all addresses used by the system must
be mapped by a local access window. This includes addresses that are mapped by PCI Express inbound
windows.
The local access window registers exist as part of the local access block in the system configuration
registers. See Section 5.2.2, “System Configuration Registers.” A detailed description of the local access
window registers is given in the following sections. Note that the minimum size of a window is 4 Kbytes,
so the low-order 12 bits of the base address cannot be specified.
5.1.3.1 Local Access Register Memory Map
Table 5-4 shows the memory map for the local access registers.
Table 5-4. Local Access Register Memory Map
Local Access—Block Base Address 0x0_0000
Local Memory
Offset (Hex)
Register Access Reset Section/Page
0x0_0000 Internal memory map base address register (IMMRBAR) R/W 0xFF40_0000 5.1.4.1/5-5
0x0_0004 Reserved — — —
0x0_0008 Alternate configuration base address register (ALTCBAR) R/W 0x0000_0000 5.1.4.2/5-7
0x0_000C–0x0_001C Reserved — — —
0x0_0020 eLBC local access window 0 base address register
(LBLAWBAR0)
R/W 0x0000_0000
1
5.1.4.3/5-7
0x0_0024 eLBC local access window 0 attribute register (LBLAWAR0) R/W 0x0000_0000
2
5.1.4.4/5-8
0x0_0028 eLBC local access window 1 base address register
(LBLAWBAR1)
R/W 0x0000_0000 5.1.4.3/5-7
0x0_002C eLBC local access window 1 attribute register (LBLAWAR1) R/W 0x0000_0000 5.1.4.4/5-8