Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
xiv Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
14.6.2 Interrupts............................................................................................................... 14-122
14.6.3 Mailbox.................................................................................................................. 14-124
14.6.4 Power Management ............................................................................................... 14-126
14.6.5 Hot Reset................................................................................................................ 14-127
14.7 Initialization/Application Information....................................................................... 14-127
14.7.1 Initialization Sequence........................................................................................... 14-127
14.8 DMA Functional Operation....................................................................................... 14-128
14.8.1 DMA Descriptor Format........................................................................................ 14-128
14.8.2 Write DMA............................................................................................................ 14-130
14.8.3 Read DMA............................................................................................................. 14-131
14.8.4 Descriptor-Based DMA......................................................................................... 14-132
Chapter 15
SerDes PHY
15.1 Introduction.................................................................................................................... 15-1
15.1.1 Overview.................................................................................................................... 15-1
15.1.2 Features...................................................................................................................... 15-1
15.1.3 Mode of Operation..................................................................................................... 15-2
15.1.4 Clock.......................................................................................................................... 15-2
15.2 External Signals ............................................................................................................. 15-2
15.3 Memory Map/Registers ................................................................................................. 15-3
15.3.1 SerDes Control Register 0 (SRDSCR0) .................................................................... 15-4
15.3.2 SerDes Control Register 1 (SRDSCR1) .................................................................... 15-6
15.3.3 SerDes Control Register 2 (SRDSCR2) .................................................................... 15-7
15.3.4 SerDes Control Register 3 (SRDSCR3) .................................................................... 15-8
15.3.5 SerDes Control Register 4 (SRDSCR4) .................................................................... 15-9
15.3.6 SerDesn Reset Control Register (SRDSRSTCTL).................................................. 15-10
15.4 Initialization Sequence and Reset................................................................................ 15-10
15.5 Power Management: Power Down .............................................................................. 15-11
Chapter 16
Enhanced Three-Speed Ethernet Controllers
16.1 Overview........................................................................................................................ 16-1
16.2 Features.......................................................................................................................... 16-2
16.3 Modes of Operation ....................................................................................................... 16-4
16.4 External Signals Description ......................................................................................... 16-5
16.4.1 Detailed Signal Descriptions ..................................................................................... 16-7
16.5 Memory Map/Register Definition ................................................................................. 16-9
16.5.1 Top-Level Module Memory Map ............................................................................ 16-10