Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-32 Freescale Semiconductor
4.5.2.3 System Clock Control Register (SCCR)
The system clock control register (SCCR), shown in Figure 4-15, controls device units that have a
configurable clock ratio.
NOTE
The SCCR is not meant for dynamic On/Off of the clock to the module. This
can be only disabled once after reset. To use the module again, a power-on
reset cycle has to take place.
Table 4-33 defines the bit fields of SCCR.
Address 0x0_0A08 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 15
R
TSEC1CM TSEC2CM SDHCCM — USBDRCM PCIEXPCM —
W
Reset 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0
16 25 26 27 28 31
R
— DMACCM —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 4-15. System Clock Control Register (SCCR)
Table 4-33. SCCR Bit Descriptions
Bits Name Description
0–1 TSEC1CM TSEC1 clock mode.
00 TSEC1 clock is disabled.
01 TSEC1 clock/csb_clk ratio is 1:1.
10 TSEC1 clock/csb_clk ratio is 1:2 (csb_clk has higher frequency than TSEC1).
11 TSEC1 clock/csb_clk ratio is 1:3 (csb_clk has higher frequency than TSEC1).
2–3 TSEC2CM TSEC2 clock mode.
00 TSEC2 clock is disabled.
01 TSEC2 clock/csb_clk ratio is 1:1.
10 TSEC2 clock/csb_clk ratio is 1:2 (csb_clk has higher frequency than TSEC2).
11 TSEC2 clock/csb_clk ratio is 1:3 (csb_clk has higher frequency than TSEC2).
4–5 SDHCCM SDHC clock mode
00 SDHC core clock is disabled.
01 SDHC core clock/csb_clk ratio is 1:1.
10 SDHC core clock/csb_clk ratio is 1:2.
11 SDHC core clock/csb_clk ratio is 1:3.
6–7 — Reserved, should be set to 0 1
8–9 USBDRCM USB DR clock mode.
00 USB DR clock is disabled.
01 USB DR clock/csb_clk ratio is 1:1.
10 USB DR clock/csb_clk ratio is 1:2 (csb_clk has higher frequency than the USB DR).
11 USB DR clock/csb_clk ratio is 1:3 (csb_clk has higher frequency than the USB DR).