Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-31
4.5.2.2 Output Clock Control Register (OCCR)
The OCCR shown in Figure 4-14, controls the device output clocks. It is possible to control some output
clock modes by writing to this memory-mapped register as described below.
Table 4-32 defines the bit fields of OCCR.
Address 0x0_0A04 Access: Read/Write
0 15
R
—
W
Reset All zeros
16 17 18 19 23 24 25 31
R
MCK0O
E, MCK_
B0OE
MCK1O
E,
MCK_B
1OE
MCK2O
E,
MCK_B
2OE
— LCLK0E —
W
Reset1110000010000000
Figure 4-14. Output Clock Control Register (OCCR)
Table 4-32. OCCR Bit Settings
Bits Name Description
0–15 — Reserved, should be cleared
16 MCK0OE,
MCK_B0OE
Enable/Disable MCK[0] pins clock out
0 Disable MCK[0] and MCK[0]
1 Enable MCK[0] and MCK
[0]
17 MCK1E,
MCK_B1OE
Enable/Disable MCK[1] pins clock out
0 Disable MCK[1] and MCK[1]
1 Enable MCK[1] and MCK[1]
18 MCK2E,
MCK_B2OE
Enable/Disable MCK[2] pins clock out
0 Disable MCK[2] and MCK
[2]
1 Enable MCK[2] and MCK
[2]
19–23 — Reserved, should be cleared
24 LCLK0E Enable/Disable LCLK[0] pin clock out
0 Disable LCLK[0]
1 Enable LCLK[0]
25–31 — Reserved, should be cleared