Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-30 Freescale Semiconductor
4.5.2.1 System PLL Mode Register (SPMR)
SPMR is shown in Figure 4-13. It obtains its values according to the reset configuration input signal and
the reset configuration word low loaded during the reset flow. Note that this register is updated only during
a power-on reset sequence and not by a hard reset sequence. It may hold values different than those in the
RCWLR after a hard reset sequence.
Table 4-31 defines the system PLL mode register bit fields.
0x0_0A08 System clock control register (SCCR) R/W 0x5550_0010 4.5.2.3/4-32
0x0_0A0C–
0x0_0AFC
Reserved, should be cleared — — —
Address 0x0_0A00 Access: Read only
0 1 234 789 15
RLBCMDDRCM
—
SPMF — COREPLL
W
Reset
1
1
See Ta ble 4 -3 1 for reset values.
n n nnnnnnnn n nnnnn
16 31
R—
W
Reset n n nnnnnnnn n nnnnn
Figure 4-13. System PLL Mode Register
Table 4-31. System PLL Mode Register Bit Settings
Bits Name Meaning Description
0 LBCM Local bus memory controller clock mode Section 4.3.2.1, “Reset Configuration Word Low
Register (RCWLR)”
1 DDRCM DDR SDRAM memory controller clock mode Section 4.3.2.1, “Reset Configuration Word Low
Register (RCWLR)”
2–3 — Reserved, should be cleared —
4–7 SPMF System PLL multiplication factor Section 4.3.2.1.2, “System PLL Configuration”
8 — Reserved —
9–15 COREPLL Core PLL configuration For more information, see MPC8308
PowerQUICC II Pro Processor Hardware
Specification.
16–31 — Reserved, should be cleared —
Table 4-30. Clock Configuration Registers Memory Map (continued)
Address Register Access Reset Section/Page