Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-29
Table 4-28 defines the bit fields of RCR.
4.5.1.7 Reset Control Enable Register (RCER)
RCER, shown in Figure 4-12, indicates by the CRE field that the RPR is accessed with a value that enables
RCR.
Table 4-29 defines the bit fields of RCER.
4.5.2 Clock Configuration Registers
The clock configuration and status registers are shown in Table 4-30.
Table 4-28. RCR Bit Settings
Bits Name Description
0–29 — Reserved, should be cleared.
30 SWHR Software hard reset. Setting this bit causes the device to begin a hard reset flow. This bit returns to its reset
state during the reset sequence, so reading it always returns all zeros.
31 — Reserved.
Address 0x0_0920 Access: User read/write
0 15
R
—
W
Reset All zeros
16 30 31
R
—CRE
W
Reset All zeros
Figure 4-12. Reset Control Enable Register (RCER)
Table 4-29. RCER Bit Settings
Bits Name Description
0–30 — Reserved, should be cleared.
31 CRE Control register enabled. When set, indicates that the RPR was accessed with a value that enables the RCR.
Writing 1 to this bit disables the RCR and clears this bit. Writing zero has no effect.
Table 4-30. Clock Configuration Registers Memory Map
Address Register Access Reset Section/Page
Reset Configuration—Block Base Address 0x0_0A00
0x0_0A00 System PLL mode register (SPMR) R 0xnnnn_nnnn 4.5.2.1/4-30
0x0_0A04 Output clock control register (OCCR) R/W 0x0000_E080 4.5.2.2/4-31