Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-28 Freescale Semiconductor
4.5.1.5 Reset Protection Register (RPR)
RPR, shown in Figure 4-10, prevents unintended software reset requests caused by writes to the reset
control register (RCR). To disable a write to the reset control register (RCR), the user should write a 1 to
RCER[CRE].
Table 4-27 defines the bit fields of RPR.
4.5.1.6 Reset Control Register (RCR)
RCR, shown in Figure 4-11, can be used by software to initiate a hard reset sequence. To allow writing to
this register, the user must enable it by writing the value 0x5253_5445 to the RPR.
Address 0x0_0918 Access: User read/write
0 15
R
RCPW
W
Reset All zeros
16 31
R
RCPW
W
Reset All zeros
Figure 4-10. Reset Protection Register (RPR)
Table 4-27. RPR Bit Descriptions
Bits Name Description
0–31 RCPW Reset control protection word. Prevents unintended software reset requests because of a write to the RCR.
The user should write the value 0x5253_5445 (RSTE in ASCII) to enable. Enable indication appears in the
reset control enable register (RCER[CRE]). Reading this register always returns all zeros.
Address 0x0_091C Access: User read/write
0 15
R
—
W
Reset All zeros
16 29 30 31
R
—SWHR—
W
Reset All zeros
Figure 4-11. Reset Control Register (RCR)