Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-27
4.5.1.4 Reset Mode Register (RMR)
RMR, shown in Figure 4-9, enables a hard reset sequence on the device when the e300 core enters
checkstop state.
Table 4-26 describes the RMR fields.
29 BMRS Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected, BMRS
is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it (writing zero
has no effect).
0 No bus monitor reset event.
1 Bus monitor reset event.
30 — Reserved
31 HRS Hard reset status. When an external or internal hard reset event is detected, HRS is set and remains
set until software clears it. HRS is cleared by writing a 1 (writing zero has no effect).
0 No hard reset event.
1 Hard reset event.
Address 0x0_0914 Access: User read/write
0 15
R
—
W
Reset All zeros
16 30 31
R
—CSRE
W
Reset All zeros
Figure 4-9. Reset Mode Register (RMR)
Table 4-26. RMR Field Descriptions
Bits Name Function
0–30 — Reserved, should be cleared.
31 CSRE Checkstop reset enable. The core can enter checkstop mode as the result of several exception conditions.
Setting CSRE configures the device to perform a hard reset sequence when the core enters checkstop state.
0 Reset not generated when core enters checkstop state.
1 Reset generated when core enters checkstop state.
Table 4-25. Reset Status Register Field Descriptions (continued)
Bits Name Description