Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-26 Freescale Semiconductor
4.5.1.3 Reset Status Register (RSR)
RSR, shown in Figure 4-8, captures various reset events in the device. The RSR accumulates reset events.
For example, because software watchdog expiration results in a hard reset, SWRS and HRS are all set after
a software watchdog reset. This register returns to its reset value only when power-on reset occurs.
Table 4-25 defines the reset status register bit fields.
Address 0x0_0910 Access: User read/write
034 14 15
R
RSTSRC — BSF
W
Reset n
1
000000000000
16 18 19 20 23 24 26 27 28 29 30 31
R
—SWHR — — CSHR
SWR
S
BMRS — HRS
W
Reset
000000000000000
0
1
The reset value of this field is determined according to the reset configuration input signals CFG_RESET_SOURCE[0:3]
sampled during the reset flow.
Figure 4-8. Reset Status Register (RSR)
Table 4-25. Reset Status Register Field Descriptions
Bits Name Description
0–3 RSTSRC Reset configuration word source. Reflects the value of CFG_RESET_SOURCE[0:3] input signals
during the reset flow. See Section 4.3.1.1, “Reset Configuration Word Source.” Changing this field has
no effect.
4–14 — Reserved, should be cleared.
15 BSF Boot sequencer fail. If set, indicates that the I
2
C boot sequencer has failed while loading the reset
configuration words. Cleared by writing a 1 to it (writing zero has no effect).
16–18 — Reserved, should be cleared.
19 SWHR Software hard reset. If set, indicates a software hard reset. SWHR is cleared by writing a 1 to it (writing
zero has no effect).
20–23 — Reserved
24–26 — Reserved, should be cleared.
27 CSHR Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled by
the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is cleared by writing a 1
to it (writing zero has no effect).
0 No enabled check stop reset event.
1 Enabled check stop reset event.
28 SWRS Software watchdog reset status. When a software watchdog expire event (which causes a reset) is
detected, SWRS is set and remains that way until the software clears it. SWRS is cleared by writing a
1 to it (writing zero has no effect).
0 No software watchdog reset event.
1 Software watchdog reset event.