Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-25
4.4.3 Ethernet Clocking
When running in RGMII mode, the reference clocks are TSECn_GTX_CLK125 and TSECn_RX_CLK
input on the eTSEC1 and eTSEC2 interface. This can either be a 2.5- or 3.3-V signal.
When running in the MII mode, the reference clocks are TSECn_TX_CLK and TSECn_RX_CLK input
on the eTSEC1 and eTSEC2 interface. This can be either a 2.5- or 3.3-V signal.
For more information, see Chapter 16, “Enhanced Three-Speed Ethernet Controllers.”
4.5 Memory Map/Register Definitions
This section presents memory maps and register descriptions for both reset and clocking.
4.5.1 Reset Configuration Register Descriptions
The reset configuration and status registers are shown in Table 4-24.
4.5.1.1 Reset Configuration Word Low Register (RCWLR)
The reset configuration word low register (RCWLR) is shown in Figure 4-3 and described in
Section 4.3.2.1, “Reset Configuration Word Low Register (RCWLR).”
4.5.1.2 Reset Configuration Word High Register (RCWHR)
The reset configuration word high register (RCWHR) is shown in Figure 4-4 and described in
Section 4.3.2.2, “Reset Configuration Word High Register (RCWHR).”
Table 4-24. Reset Configuration and Status Registers Memory Map
Address Register Access Reset Section/Page
Reset Configuration—Block Base Address 0x0_0900
0x0_0900 Reset configuration word low register (RCWLR) R 0x0000_0000 4.5.1.1/4-25
0x0_0904 Reset configuration word high register (RCWHR) R 0x0000_0000 4.5.1.2/4-25
0x0_0908–
0x0_090C
Reserved, should be cleared — — —
0x0_0910 Reset status register (RSR) R/W 0x0000_0000 4.5.1.3/4-26
0x0_0914 Reset mode register (RMR) R/W 0x0000_0000 4.5.1.4/4-27
0x0_0918 Reset protection register (RPR) R/W 0x0000_0000 4.5.1.5/4-28
0x0_091C Reset control register (RCR) R/W 0x0000_0000 4.5.1.6/4-28
0x0_0920 Reset control enable register (RCER) R/W 0x0000_0000 4.5.1.7/4-29
0x0_0924 Reserved. — — —
0x0_0928–
0x0_09FC
Reserved, should be cleared — — —