Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-24 Freescale Semiconductor
The csb_clk frequency is derived as follows:
csb_clk = [SYS_CLK_IN] × SPMF
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is
loaded at power-on reset or by one of the hard-coded reset options. See Section 4.3, “Reset Configuration.”
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock output (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV].
See Section 10.1.3.1, “eLBC Bus Clock and Clock Ratios,” for more information.
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory-mapped
register after the device comes out of reset. Table 4-23 specifies which units have a configurable clock
frequency. For more information, see Section 4.5.2.3, “System Clock Control Register (SCCR).”
NOTE
The clock ratios of these units must be set before they are accessed.
eTSEC1 and eTSEC2 share the same clock control, and therefore the same
clock ratio. They can be independently switched off.
4.4.2 USB Clocking
The clock signal (USBDR_CLK) is given from an external source. For more details refer to Chapter 13,
“Universal Serial Bus Interface.”
Table 4-23. Configurable Clock Units
Unit Default Frequency Options
eTSEC1 and eTSEC2 csb_clk Off, csb_clk, csb_clk/2, csb_clk/3
I
2
C csb_clk Off, csb_clk, csb_clk/2, csb_clk/3
USB DR csb_clk Off, csb_clk, csb_clk/2, csb_clk/3
DMA csb_clk Off, csb_clk, csb_clk/2, csb_clk/3
PCIEXP csb_clk Off, csb_clk
eSDHC csb_clk Off, csb_clk, csb_clk/2, csb_clk/3