Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-23
Figure 4-7 shows the internal distribution of clocks within the device.
Figure 4-7. Clock Subsystem Block Diagram
4.4.1 System Clock Domains
As shown in Figure 4-7, the primary clock input (SYS_CLK_IN) frequency is multiplied up by the system
phase-locked loop (PLL) and the clock unit to create three major clock domains:
• The coherent system bus clock (csb_clk)
• The internal clock for the DDR controller (ddr_clk)
• The internal clock for the local bus interface unit (lbc_clk)
PCI Express
e300 Core
System
PLL
e300
PLL
Clk
Gen
125/100 MHz
PLL
fbref
SYS_CLK_IN
PCVTR Mux
Protocol
Converter
SerDes PHY
+
-
24–66 MHz
SD_REF_CLK_B
SD_REF_CLK
MPC8308
eTSEC1
TSEC1_RX_CLK
TSEC1_TX_CLK/
TSEC1_GTX_CLK125
DDR
Clock
/2
Divider
/n
csb_clk
LBC
Clock
Divider
clk tree
MCK[0:2]
MCK[0:2]
DDR
Memory
Device
Local
Bus
Memory
Device
ddr_clk
lbc_clk
eSDHC
SD_CLK
RTC_PIT_CLOCK
RTC
Sys Ref
(32 KHz)
USBDR_CLK USB
TSEC2_RX_CLK
TSEC2_TX_CLK/
TSEC2_GTX_CLK125
eTSEC2