Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-22 Freescale Semiconductor
Table 4-22 defines the hard-coded reset configuration word high fields values. These values select
hard-coded reset configuration words options, as described in Section 4.3.1.1, “Reset Configuration Word
Source.”
4.4 Clocking
The following external clock sources are utilized on MPC8308:
• System clock (SYS_CLK_IN)
• Ethernet Clock (TSECn_RX_CLK/TSECn_TX_CLK/TSECn_GTX_CLK125 for eTSEC1 and
eTSEC2)
• USB clock (USBDR_CLK for ULPI)
• Real-time clock (RTC_PIT_CLOCK)
• SerDes PHY clock
• eSDHC clock (SD_CLK)
For more information, see Chapter 15, “SerDes PHY.”
All clock inputs can be supplied using an external canned oscillator, a clock generation chip, or some other
source that provides a standard CMOS square wave input.
Table 4-22. Hard-Coded Reset Configuration Word High Field Values
Bits Name
Field Values when CFG_RESET_SOURCE[0–3] =
1000–1100
Meaning
1000 1001 1010 1011 1100
0–3 Reserved 0000 —
4 COREDIS 0 0 1 0 0 e300 core is disabled (boot hold-off)
5 BMS 1 Boot memory space is 0xFF80_0000–
0xFFFF_FFFF. MSR[IP] initial value is 0b1.
6–7 BOOTSEQ 00 Boot sequencer is disabled
8 SWEN 0 Software watchdog disabled
9–11 ROMLOC 110 Boot ROM interface location
12–13 RLEXT 00 Legacy mode
14–15 Reserved 00 —
16–18 TSEC1M 000 011 011 000 011 000 = MII mode
011 = RGMII mode
19–21 TSEC2M 000 011 011 000 011
22–27 Reserved 000000 —
28 TLE 0 Big-endian mode
29–31 Reserved 000 —