Information

Reset, Clocking, and Initialization

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 4-21

4.3.3.2.4 Reset Configuration Load Fail

Failure of reset configuration load by the I

C boot sequencer can be caused by an incorrect EEPROM data

structure or I

C bus problem. If a reset configuration load failure occurs, due to preamble fail or any other

C bus error detection, the device continuously attempts to reload the hard reset configuration words from

the I

C bus. The device does not negate HRESET and remains in hard reset state until the RCWs are

successfully loaded or the PORESET flow is restarted.

4.3.3.3 Default Reset Configuration Words

If the device is configured not to load the reset configuration words from NOR Flash, NAND Flash, or an

C EEPROM, it can also be initialized with one of five hard-coded default options, selected by the reset

configuration input signals, CFG_RESET_SOURCE[0:3].

The reset configuration words are driven internally with the values shown in Table 4-20, Table 4-21, and

Table 4-22.

Table 4-20. RCW Values Corresponding to Hard Coded Options

CFG_RESET_SOURCE[0:3] RCWLR[0:31] RCWHR[0:31]

4'b1000 32'h4504_0000 32'h0460_0000

4'b1001 32'h4404_0000 32'h0460_6C00

4'b1010 32'h4405_0000 32'h0C60_6C00

4'b1011 32'h4406_0000 32'h0460_0000

4'b1100 32'h4406_0000 32'h0460_6C00

Table 4-21. Hard Coded Reset Configuration Word Low Fields Values

RCWLR

Bit 0 1 2–3 4–7 8 9–10 11–15 16–31

Definition LBCM DDRCM SVCOD SPMF Reserve CVCOD CPMF Reserve

RCWLR = 32'h4423_0000 (sysclk = 31.25)

Value 0 1 00 0100 0 01 00011 0

Comment csb_clk csb_clkx2 spll_out x2 4:1 — cpll_out x4 1.5:1 —

Frequency 125 250 500 125 — 750 187.5 —

RCWLR = 32'h4404_0000 (sysclk = 33.33)

Value 0 1 00 0100 0 00 00100 0

Comment csb_clk csb_clkx2 spll_out x2 4:1 — cpll_out x2 2:1 —

Frequency 133 266 533 133 — 533 266 —