Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-17
Table 4-17 shows addresses that should be used to contain the reset configuration words. Byte addresses
that do not appear in this table have no effect on the configuration of the device. The values of the bytes
in Table 4-17 are always read on byte lane LD[0:7] regardless of the port size.
.
Table 4-18 shows the data structure of the local bus device containing the reset configuration words
(RCWL and RCWH).
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4.3.3.1.1 Local Bus Controller Setting
The device uses GPCM to load the reset configuration from EEPROM or NOR Flash. The device reads 64
bytes in this case. The local bus controller’s registers setting is set according to Table 4-19.
Table 4-17. Local Bus Configuration EEPROM Addresses
Reset Configuration Word Bits [0:7] Address Bits [8:15] Address Bits [16:23] Address Bits [24:31] Address
Low 0x00 0x08 0x10 0x18
High 0x20 0x28 0x30 0x38
Table 4-18. Local Bus Reset Configuration Words Data Structure
EEPROM Address
EEPROM Data Bits
[0:7] [8:15] [16:23] [24:31]
0x00 RCWL[0:7]
0x04
0x08 RCWL[8:15]
0x0C
0x10 RCWL[16:23]
0x14
0x18 RCWL[24:31]
0x1C
0x20 RCWH[0:7]
0x24
0x28 RCWH[8:15]
0x2C
0x30 RCWH[16:23]
0x34
0x38 RCWH[24:31]
0x3C