Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-16 Freescale Semiconductor
4.3.2.2.5 eTSEC2 Mode
The eTSEC2 mode reset configuration word field, shown in Table 4-15, selects the protocol used by the
eTSEC2 controller.
4.3.2.2.6 e300 Core True Little-Endian
The true little-endian reset configuration word field, shown in Table 4-16, selects whether the e300 core
operates in big-endian mode or true little-endian mode at reset.
4.3.3 Loading the Reset Configuration Words
The device loads the reset configuration words from a local bus EEPROM, a local bus NAND Flash, or an
I
2
C serial EEPROM, or uses hard-coded configuration, as selected by the reset configuration inputs
described in Section 4.3.1, “Reset Configuration Signals.” The following sections describe each of these
options.
4.3.3.1 Loading from Local Bus
The reset configuration words are assumed to reside in an EEPROM or NOR Flash or NAND Flash device
connected to LCS0
of the device local bus. Because the port size of this EEPROM is unknown, the device
reads all configuration words byte-by-byte only from locations that are independent of port size.
Table 4-15. eTSEC2 Mode Configuration
Reset Configuration
Word High Register
(RCWHR) Bits
Field Name
Value
(Binary)
Meaning
19–21 TSEC2M 000 The eTSEC2 controller operates in the MII protocol, using only four
transmit data signals and four receive data signals.
001 Reserved
010 Reserved
011 The eTSEC2 controller operates in the RGMII protocol, using four
transmit data signals and four receive data signals.
100 Reserved
101 Reserved
110 Reserved
111 Reserved
Table 4-16. e300 Core True Little-Endian
Reset Configuration
Word High Register
(RCWHR) Bit
Field Name
Value
(Binary)
Meaning
28 TLE 0 Big-endian mode
1 True little-endian mode