Information

Revision History
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
B-2 Freescale Semiconductor
Section 4.5.1.3, “Reset Status
Register (RSR)”
In the reset value footnote and bit description of the RSTSRC bit, updated the reset
configuration input signals name to “CFG_RESET_SOURCE[0:3]”.
Figure 4-7, Clock Subsystem Block
Diagram
Updated the figure.
Tabl e 4-23, Configurable Clock Units Removed options “csb_clk/2, csb_clk/3” from the PCIEXP unit.
System Configuration
Table 5-18, System Configuration
Register Memory Map
Figure 5-16, DDR Control Driver
Register (DDRCDR)
Updated reset value of ‘DDR control driver register (DDRCDR)’ from 0x7304_0001 to
0x0000_0000.
Table 5-25, SICRL Bit Settings For the “IRQ[3]” pin, changed the “Pin Function 3” value from “—” to “INTA
”.
Table 5-18, System Configuration
Register Memory Map
Updated the reset value of “System part and revision ID register (SPRIDR)” to 8101_01nn.
Table 5-23, REVID Coding Added a row for REVID “0x11”.
Table 5-26, SICRH Bit Settings Added the following footnote on the “SD_CLK” pin:
“Clock pulses may be observed on SD_CLK pin after reset until GPIO_16 is selected by
setting SICRH[eSDHC_A]=0b11.
Table 5-52, PTEVR Bit Settings Updated the bit description of the PTEVR[PIF] bit.
Table 5-54, GTM External
Signals—Detailed Signal
Descriptions
Updated the description of the TOUT
n signal.
Arbiter and Bus Monitor
Tabl e 6-1, Arbiter Register Map
Section 6.2.3, “Arbiter Event Enable
Register (AEER)”
Added AEER register.
Figure 6-7, Arbiter Event Attributes
Register (AEATR)
Figure 6-8, Arbiter Event Address
Register (AEADR)
Updated register access to “Read only”.
e300 Processor Core Overview
Tabl e 7-1, Device Revision Level
Cross-Reference
Updated the table.
Tabl e 7-3, e300 HID0 Bit
Descriptions
In the bit descriptions of bits EBA and EBD, added the note “Do not set this bit; the CSB
does not have parity signals.
Integrated Programmable Interrupt Controller (IPIC)
Table B-1. Changes from Revision 0 to Revision 1
Section #
(Fig #/title
Table#/title)
Description