Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-15
bits, as shown in Table 4-10. Accesses to the boot vector and the default boot ROM region of the local
address map are directed to the interface specified by this field.
The local access window of the selected boot ROM interface is enabled and initialized with the proper base
address and size, as described in Section 5.1, “Local Memory Map Overview and Example.”
4.3.2.2.4 eTSEC1 Mode
The TSEC1 mode reset configuration word field, shown in Table 4-14, selects the protocol used by the
enhanced three-speed Ethernet controller interface (eTSEC1) controller.
Table 4-13. Boot ROM Location
RCWHR
Bits
Field Name
Value
(Binary)
Meaning
Legacy Mode (RLEXT = 00) NAND Flash Mode (RLEXT = 01)
9–11 ROMLOC 000 DDR SDRAM Reserved
001 Reserved Local bus NAND Flash—8-bit small page
ROM
010 Reserved Reserved
011 Reserved Reserved
100 Reserved Reserved
101 Local bus GPCM—8-bit ROM Local bus NAND Flash—8-bit large page
ROM
110 Local bus GPCM—16-bit ROM Reserved
111 Reserved Reserved
Table 4-14. eTSEC1 Mode Configuration
Reset Configuration
Word High Register
(RCWHR) Bits
Field Name
Value
(Binary)
Meaning
16–18 TSEC1M 000 The eTSEC1 controller operates in the MII protocol, using only four
transmit data signals and four receive data signals.
001 Reserved
010 Reserved
011 The eTSEC1 controller operates in the RGMII protocol, using four
transmit data signals and four receive data signals.
100 Reserved
101 Reserved
110 Reserved
111 Reserved