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1161

Complete List of Configuration, Control, and Status Registers

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

A-30 Freescale Semiconductor

0xC60 Reserved — — —

0xC64 RFBPTR4*—Last Free RxBD pointer for ring 4 R/W 0x0000_0000 16.5.3.9.2/16-108

0xC68 Reserved — — —

0xC6C RFBPTR5*—Last Free RxBD pointer for ring 5 R/W 0x0000_0000 16.5.3.9.2/16-108

0xC70 Reserved — — —

0xC74 RFBPTR6*—Last Free RxBD pointer for ring 6 R/W 0x0000_0000 16.5.3.9.2/16-108

0xC78 Reserved — — —

0xC7C RFBPTR7*—Last Free RxBD pointer for ring 7 R/W 0x0000_0000 16.5.3.9.2/16-108

eTSEC Future Expansion Space

0xCC0–

0xD94

Reserved — — —

eTSEC IEEE 1588 Registers

0xE00 TMR_CTRL* - Timer control register R/W 0x0001_0001 16.5.3.10.1/16-109

0xE04 TMR_TEVENT* - time stamp event register w1c 0x0000_0000 16.5.3.10.2/16-111

0xE08 TMR_TEMASK* - Timer event mask register R/W 0x0000_0000 16.5.3.10.3/16-113

0xE0C TMR_PEVENT* - time stamp event register R/W 0x0000_0000 16.5.3.10.4/16-113

0xE10 TMR_PEMASK* - Timer event mask register R/W 0x0000_0000 16.5.3.10.5/16-114

0xE14 TMR_STAT* - time stamp status register R/W 0x0000_0000 16.5.3.10.6/16-115

0xE18 TMR_CNT_H* - timer counter high register R/W 0x0000_0000 16.5.3.10.7/16-115

0xE1C TMR_CNT_L* - timer counter low register R/W 0x0000_0000 16.5.3.10.7/16-115

0xE20 TMR_ADD* - Timer drift compensation addend register R/W 0x0000_0000 16.5.3.10.8/16-116

0xE24 TMR_ACC* - Timer accumulator register R/W 0x0000_0000 16.5.3.10.9/16-117

0xE28 TMR_PRSC* -Timer prescale R/W 0x0000_0002 16.5.3.10.10/16-117

0xE2C Reserved — — —

0xE30 TMROFF_H* - Timer offset high R/W 0x0000_0000 16.5.3.10.11/16-118

0xE34 TMROFF_L* - Timer offset low R/W 0x0000_0000 16.5.3.10.11/16-118

0xE40 TMR_ALARM1_H* - Timer alarm 1 high register R/W 0xFFFF_FFFF 16.5.3.10.12/16-118

0xE44 TMR_ALARM1_L* - Timer alarm 1 high register R/W 0xFFFF_FFFF

0xE48 TMR_ALARM2_H* - Timer alarm 2 high register R/W 0xFFFF_FFFF

0xE4C TMR_ALARM2_L* - Timer alarm 2 high register R/W 0xFFFF_FFFF

0xE50–

0xE7C

Reserved — — —

Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued)

eTSEC 1—Block Base Address 0x2_4000

eTSEC 2—Block Base Address 0x2_5000

eTSEC1

Offset

Name

Access

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