Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
A-28 Freescale Semiconductor
0x6F8 TEDF—Transmit excessive deferral packet counter R/W 0x0000_0000 16.5.3.6.31/16-92
0x6FC TSCL—Transmit single collision packet counter R/W 0x0000_0000 16.5.3.6.32/16-93
0x700 TMCL—Transmit multiple collision packet counter R/W 0x0000_0000 16.5.3.6.33/16-93
0x704 TLCL—Transmit late collision packet counter R/W 0x0000_0000 16.5.3.6.34/16-94
0x708 TXCL—Transmit excessive collision packet counter R/W 0x0000_0000 16.5.3.6.35/16-94
0x70C TNCL—Transmit total collision counter R/W 0x0000_0000 16.5.3.6.36/16-95
0x710 Reserved — — —
0x714 TDRP—Transmit drop frame counter R/W 0x0000_0000 16.5.3.6.37/16-95
0x718 TJBR—Transmit jabber frame counter R/W 0x0000_0000 16.5.3.6.38/16-96
0x71C TFCS—Transmit FCS error counter R/W 0x0000_0000 16.5.3.6.39/16-96
0x720 TXCF—Transmit control frame counter R/W 0x0000_0000 16.5.3.6.40/16-97
0x724 TOVR—Transmit oversize frame counter R/W 0x0000_0000 16.5.3.6.41/16-97
0x728 TUND—Transmit undersize frame counter R/W 0x0000_0000 16.5.3.6.42/16-98
0x72C TFRG—Transmit fragments frame counter R/W 0x0000_0000 16.5.3.6.43/16-98
eTSEC Counter Control and TOE Statistics Registers
0x730 CAR1—Carry register one register
3
w1c 0x0000_0000 16.5.3.6.44/16-99
0x734 CAR2—Carry register two register
3
w1c 0x0000_0000 16.5.3.6.45/16-100
0x738 CAM1—Carry register one mask register R/W 0xFE03_FFFF 16.5.3.6.46/16-101
0x73C CAM2—Carry register two mask register R/W 0x000F_FFFD 16.5.3.6.47/16-103
0x740 RREJ*—Receive filer rejected packet counter R/W 0x0000_0000 16.5.3.6.48/16-104
0x744–
0x7FC
Reserved — — —
Hash Function Registers
0x800 IGADDR0—Individual/group address register 0 R/W 0x0000_0000 16.5.3.7.1/16-105
0x804 IGADDR1—Individual/group address register 1 R/W 0x0000_0000
0x808 IGADDR2—Individual/group address register 2 R/W 0x0000_0000
0x80C IGADDR3—Individual/group address register 3 R/W 0x0000_0000
0x810 IGADDR4—Individual/group address register 4 R/W 0x0000_0000
0x814 IGADDR5—Individual/group address register 5 R/W 0x0000_0000
0x818 IGADDR6—Individual/group address register 6 R/W 0x0000_0000
0x81C IGADDR7—Individual/group address register 7 R/W 0x0000_0000
0x820–
0x87C
Reserved — — —
Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued)
eTSEC 1—Block Base Address 0x2_4000
eTSEC 2—Block Base Address 0x2_5000
eTSEC1
Offset
Name
1
Access
2
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