Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-25
0x430 Reserved — — —
0x434 RBASE6*—RxBD base address of ring 6 R/W 0x0000_0000 16.5.3.3.11/16-60
0x438 Reserved — — —
0x43C RBASE7*—RxBD base address of ring 7 R/W 0x0000_0000 16.5.3.3.11/16-60
0x440–
0x4BC
Reserved — — —
0x4C0 TMR_RXTS_H* - Rx timer time stamp register high R/W 0x0000_0000 16.5.3.3.12/16-61
0x4C4 TMR_RXTS_L* - Rx timer time stamp register low R/W 0x0000_0000 16.5.3.3.12/16-61
0x4C8–
0x4FC
Reserved — — —
eTSEC MAC Registers
0x500 MACCFG1—MAC configuration register 1 R/W 0x0000_0000 16.5.3.5.1/16-64
0x504 MACCFG2—MAC configuration register 2 R/W 0x0000_7000 16.5.3.5.2/16-66
0x508 IPGIFG—Inter-packet/inter-frame gap register R/W 0x4060_5060 16.5.3.5.3/16-68
0x50C HAFDUP—Half-duplex control R/W 0x00A1_F037 16.5.3.5.4/16-69
0x510 MAXFRM—Maximum frame length R/W 0x0000_0600 16.5.3.5.5/16-70
0x514–
0x51C
Reserved — — —
0x520 MIIMCFG—MII management configuration R/W 0x0000_0007 16.5.3.5.6/16-70
0x524 MIIMCOM—MII management command R/W 0x0000_0000 16.5.3.5.7/16-71
0x528 MIIMADD—MII management address R/W 0x0000_0000 16.5.3.5.8/16-72
0x52C MIIMCON—MII management control WO 0x0000_0000 16.5.3.5.9/16-72
0x530 MIIMSTAT—MII management status R 0x0000_0000 16.5.3.5.10/16-73
0x534 MIIMIND—MII management indicator R 0x0000_0000 16.5.3.5.11/16-73
0x538 Reserved — — —
0x53C IFSTAT—Interface status R 0x0000_0000 16.5.3.5.12/16-74
0x540 MACSTNADDR1—MAC station address register 1 R/W 0x0000_0000 16.5.3.5.13/16-74
0x544 MACSTNADDR2—MAC station address register 2 R/W 0x0000_0000 16.5.3.5.14/16-75
Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued)
eTSEC 1—Block Base Address 0x2_4000
eTSEC 2—Block Base Address 0x2_5000
eTSEC1
Offset
Name
1
Access
2
Reset Section/Page