Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-14 Freescale Semiconductor
4.3.2.2.2 Boot Sequencer Configuration
The boot sequencer configuration options, shown in Table 4-12, allow the boot sequencer to load
configuration data from the serial ROM located on the I
2
C port before the host tries to configure the device.
These options also specify normal or extended I
2
C addressing modes. See Section 17.4.5, “Boot
Sequencer Mode.”
NOTE
When the boot sequencer is enabled, the e300 core must be prevented from
fetching boot code by setting the core disable reset configuration word field
(COREDIS) as described in Section 4.3.2.2, “Reset Configuration Word
High Register (RCWHR).” If the e300 core is required to proceed, the boot
sequencer should enable boot vector fetch by clearing ACR[COREDIS] as
described in Section 6.2.1, “Arbiter Configuration Register (ACR).”
4.3.2.2.3 Boot ROM Location
The device defines the default boot ROM address range to be 8 Mbytes at addresses 0x0000_0000 to
0x007F_FFFF or 0xFF80_0000 to 0xFFFF_FFFF (selected by the BMS reset configuration word field).
However, the on-chip peripheral that manages these boot ROM accesses can be selected at power up.
The boot ROM location reset configuration word field, shown in Table 4-13, establishes the location of
boot ROM. The exact boot ROM location table to be used is defined by the setting of RCWHR[RLEXT]
Table 4-12. Boot Sequencer Configuration
RCWHR Bits Field Name
Value
(Binary)
Meaning
6–7 BOOTSEQ 00 Boot sequencer is disabled. No I
2
C ROM is accessed.
01 Normal I
2
C addressing mode is used. Boot sequencer is enabled and loads
configuration information from a ROM on the I
2
C interface. A valid ROM must be
present.
10 Extended I
2
C addressing mode is used. Boot sequencer is enabled and loads
configuration information from a ROM on the I
2
C interface. A valid ROM must be
present.
11 Reserved, should be cleared.