Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-23
0x214 TBASE2*—TxBD base address of ring 2 R/W 0x0000_0000 16.5.3.2.9/16-45
0x218 Reserved
0x21C TBASE3*—TxBD base address of ring 3 R/W 0x0000_0000 16.5.3.2.9/16-45
0x220 Reserved
0x224 TBASE4*—TxBD base address of ring 4 R/W 0x0000_0000 16.5.3.2.9/16-45
0x228 Reserved
0x22C TBASE5*—TxBD base address of ring 5 R/W 0x0000_0000 16.5.3.2.9/16-45
0x230 Reserved
0x234 TBASE6*—TxBD base address of ring 6 R/W 0x0000_0000 16.5.3.2.9/16-45
0x238 Reserved
0x23C TBASE7*—TxBD base address of ring 7 R/W 0x0000_0000 16.5.3.2.9/16-45
0x240–
0x27C
Reserved
0x280 TMR_TXTS1_ID* - Tx time stamp identification (set 1) R/W 0x0000_0000 16.5.3.2.10/16-45
0x284 TMR_TXTS2_ID* - Tx time stamp identification (set 2) R/W 0x0000_0000 16.5.3.2.10/16-45
0x288–
0x2BC
Reserved —
0x2C0 TMR_TXTS1_H* - Tx time stamp high (set 1) R/W 0x0000_0000 16.5.3.2.11/16-46
0x2C4 TMR_TXTS1_L* - Tx time stamp high (set 1) R/W 0x0000_0000 16.5.3.2.11/16-46
0x2C8 TMR_TXTS2_H* - Tx time stamp high (set 2) R/W 0x0000_0000 16.5.3.2.11/16-46
0x2CC TMR_TXTS2_L* - Tx time stamp high (set 2) R/W 0x0000_0000 16.5.3.2.11/16-46
0x2D0–
0x2FC
Reserved —
eTSEC Receive Control and Status Registers
0x300 RCTRL—Receive control register R/W 0x0000_0000 16.5.3.3.1/16-46
0x304 RSTAT—Receive status register w1c 0x0000_0000 16.5.3.3.2/16-48
0x308–
0x30C
Reserved
0x310 RXIC—Receive interrupt coalescing register R/W 0x0000_0000 16.5.3.3.3/16-50
0x314 RQUEUE*—Receive queue control register. R/W 0x0080_0080 16.5.3.3.4/16-51
0x318–
0x32C
Reserved
0x330 RBIFX*—Receive bit field extract control register R/W 0x0000_0000 16.5.3.3.5/16-52
0x334
RQFAR*—Receive queue filing table address register R/W 0x0000_0000 16.5.3.3.6/16-53
Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued)
eTSEC 1—Block Base Address 0x2_4000
eTSEC 2—Block Base Address 0x2_5000
eTSEC1
Offset
Name
1
Access
2
Reset Section/Page